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| 3. |
- Grimm, Christoph, et al.
(författare)
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C-Based Design of Embedded Systems - Editorial
- 2008
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Ingår i: EURASIP Journal on Embedded Systems. - : Springer Science and Business Media LLC. - 1687-3955 .- 1687-3963. ; :1, s. 243890-
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
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| 4. |
- Jantsch, Axel, et al.
(författare)
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Models of computation and languages for embedded system design
- 2005
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Ingår i: IEE Proceedings - Computers and digital Techniques. - : Institution of Engineering and Technology (IET). - 1350-2387 .- 1359-7027. ; 152:2, s. 114-129
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Tidskriftsartikel (refereegranskat)abstract
- Models of computation (MoC) are reviewed and organised with respect to the time abstraction they use. Continuous time, discrete time, synchronous and untimed MoCs are distinguished. System level models serve a variety of objectives with partially contradicting requirements. Consequently, it is argued that different MoCs are necessary for the various tasks and phases in the design of an embedded system. Moreover, different MoCs have to be integrated to provide a coherent system modelling and analysis environment. The relation between some popular languages and the reviewed MoCs is discussed to find that a given MoC is offered by many languages and a single language can support multiple MoCs. It is contended that it is of importance for the quality of tools and overall design productivity, which abstraction levels and which primitive operators are provided in a language. However, it is observed that there are various flexible ways to do this, e.g. by way of heterogeneous frameworks, coordination languages and embedding of different MoCs in the same language.
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| 5. |
- Khatib, Iyad Al, et al.
(författare)
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A multiprocessor system-on-chip for real-time biomedical monitoring and analysis : ECG prototype architectural design space exploration
- 2008
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Ingår i: ACM Transactions on Design Automation of Electronic Systems. - : Association for Computing Machinery (ACM). - 1084-4309 .- 1557-7309. ; 13:2, s. 31-
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Tidskriftsartikel (refereegranskat)abstract
- In this article we focus on multiprocessor system-on-chip (MPSoC) architectures for human heart electrocardiogram (ECG) real time analysis as a hardware/software (HW/SW) platform offering an advance relative to state-of-the-art solutions. This is a relevant biomedical application with good potential market, since heart diseases are responsible for the largest number of yearly deaths. Hence, it is a good target for an application-specific system-on-chip (SoC) and HW/SW codesign. We investigate a symmetric multiprocessor architecture based on STMicroelectronics VLIW DSPs that process in real time 12-lead ECG signals. This architecture improves upon state-of-the-art SoC designs for ECG analysis in its ability to analyze the full 12 leads in real time, even with high sampling frequencies, and its ability to detect heart malfunction for the whole ECG signal interval. We explore the design space by considering a number of hardware and software architectural options. Comparing our design with present-day solutions from an SoC and application point-of-view shows that our platform can be used in real time and without failures.
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| 6. |
- Lu, Zhonghai, et al.
(författare)
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Admitting and ejecting flits in wormhole-switched networks on chip
- 2007
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Ingår i: Iet Computers and Digital Techniques. - : Institution of Engineering and Technology (IET). - 1751-8601. ; 1:5, s. 546-556
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Tidskriftsartikel (refereegranskat)abstract
- Reducing the design complexity of switches is essential for cost reduction and power saving in on-chip networks. In wormhole-switched networks, packets are split into flits which are then admitted into and delivered in the network. When reaching destinations, flits are ejected from the network. Since flit admission, flit delivery and flit ejection interfere with each other directly and indirectly, techniques for admitting and ejecting flits exert a significant impact on network performance and switch cost. Different flit-admission and flit-ejection micro-architectures are investigated. In particular, for flit admission, a novel coupling scheme which binds a flit-admission queue with a physical channel (PC) is presented. This scheme simplifies the switch crossbar from 2p x p to (p + 1) x p, where p is the number of PCs per switch. For flit ejection, a p-sink model that uses only p flit sinks to eject flits is proposed. In contrast to an ideal ejection model which requires p . v flit sinks (v is the number of virtual channels per PC), the buffering cost of flit sinks becomes independent of v. The proposed flit-admission and flit-ejection schemes are evaluated with both uniform and locality traffic in a 2D 4 x 4 mesh network. The results show that both schemes do not degrade network performance in terms of average packet latency and throughput if the flit injection rate is slower than 0.57 flit/cycle/node.
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| 7. |
- Lu, Zhonghai, et al.
(författare)
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Network-on Chip Micro-Benchmarks
- 2008
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Ingår i: Embedded Systems Design. ; :September
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Tidskriftsartikel (refereegranskat)abstract
- The rapid development of Network-on-Chip (NoC) calls for a systematic approach to evaluate and fairly compare various NoC architectures. In this specification, we define a generic NoC architecture, a comprehensive set of synthetic workloads as micro-benchmarks, workload scenarios and evaluation criteria. These micro-benchmarks enable measuring particular properties of NoC architectures, complementing application benchmarks.
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| 8. |
- Lu, Zhonghai, et al.
(författare)
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TDM virtual-circuit configuration for network-on-chip
- 2008
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - 1063-8210 .- 1557-9999. ; 16:8, s. 1021-1034
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Tidskriftsartikel (refereegranskat)abstract
- In network-on-chip (NoC), time-division-multiplexing (TDM) virtual circuits (VCs) have been proposed to satisfy the quality-of-service requirements of applications. TDM VC is a connection-oriented communication service by which two or more connections take turns to share buffers and link bandwidth using dedicated time slots. In the paper, we first give a formulation of the multinode VC configuration problem for arbitrary NoC topologies. A multinode VC allows multiple source and destination nodes on it. Then we address the two problems of path selection and slot allocation for TDM VC configuration. For the path selection, we use a backtracking algorithm to explore the path diversity, constructively searching the solution space. In the slot allocation phase, overlapped VCs must be configured such that no conflict occurs and their bandwidth requirements are satisfied. We define the concept of a logical network (LN) as an infinite set of associated (time slot, buffer) pairs with respect to a buffer on a given VC. Based on this concept, we develop and prove theorems that constitute sufficient and necessary conditions to establish conflict-free VCs. They are applicable for networks where all nodes operate with the same clock frequency but allowing different phases. Using these theorems, slot allocation for VCs is a procedure of assigning VCs to different LNs. TDM VC configuration can thus be predictable and correct-by-construction. Our experiments on synthetic and real applications validate the effectiveness and efficiency of our approach.
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| 9. |
- Marinissen, E. J., et al.
(författare)
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Conference reports : DATE 07 workshop on diagnostic services in NoCs
- 2007
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Ingår i: IEEE Design & Test of Computers. - 0740-7475 .- 1558-1918. ; 24:5, s. 510-
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Tidskriftsartikel (refereegranskat)abstract
- 1. TTTC Forum honors Melvin Breuer - at the 2006 International Test Conference, a half-day technical forum was held to honor Melvin Breuer, a pioneer in the areas of VLSI design automation and test; 2. Design flow and methodology addressed at SOC 2006 - The International Symposium on System-on-Chip took place on 13-16 November 2006 in Tampere, Finland. The theme was "SoC Design Flow and Methodology." There were nine high-caliber, 45-minute invited talks, covering different approaches and application areas in SoC design.
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| 10. |
- Mathaikutty, Deepak A., et al.
(författare)
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SML-Sys : a functional framework with multiple models of computation for modeling heterogeneous system
- 2008
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Ingår i: Design automation for embedded systems. - : Springer Science and Business Media LLC. - 0929-5585 .- 1572-8080. ; 12:1-2, s. 1-30
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Tidskriftsartikel (refereegranskat)abstract
- System-on-Chip and other complex distributed hardware/software systems contain heterogeneous components. High-level modeling of such systems require frameworks that provide designers with the ability to express concepts of models of computation (MoC)s as modeling constructs. Many system-level modeling frameworks and corresponding modeling notations such as Ptolemy II and SystemC-H facilitate multi-MoC modeling but are based on imperative programming languages (C++, Java, etc). In such frameworks, the computation and communication aspects between the components of models get intertwined thereby hindering its amenability to formal analysis. In this work, we illustrate function-based semantic definitions of MoCs, which are formulated in a functional framework called SML-Sys. We illustrate through a number of examples how to create system models using this functional programming paradigm.
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